VLSI Design-II

Mr. Ashish Gambhir, Asst. Prof., ECE Department, Dronacharya College of Engineering, Gurgaon attended a Short Term Course on VLSI Design-II from 26 Dec 13 – 28 Dec 2013 organized by Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology, Bhopal. The course was sponsored by TEQIP-II (Technical Education Quality Improvement Program-Phase II) by AICTE, New Delhi.

The aim of the course was to give an overview and hands-on experience to the participants on the state-of-the art EDA tools and Synopsys tool for VLSI Design. This course comprised introductory talks delivered by experts of Cadence and Synopsys. Digital Systems Design using Verilog was followed by hands-on training on CMOS Analog and Digital design. The participants were given an exposure to the Full Custom Analog Design Flow consisting of Schematic design & Simulation, Custom Layout design, DRC/LVS, Extraction with Post Layout Simulation with hands-on session on the designs and a real experience of using the standard cell design flow, Floor-plan, P&R etc. which is required for ASIC design in Digital domain using Cadence tools. Synopsys provides a comprehensive portfolio of tools for digital and mixed-signal IC design, implementation, sign-off, verification, test, and Design-For-Manufacturability (DFM). The course also had lab sessions for complete understanding of tool and circuits.

The three day course started with the introduction to VLSI Design and the application and research areas in VLSI. The experts laid the foundations of Digital Systems Design using Front End software tool Xilinx ISE 13.2i and ModelSim. Basics of programming in Verilog were covered and a set of 5 demonstrations were given on the Xilinx synthesis tool and ModelSim simulator assisting the theory part. The second day of the course covered the backend design of ASICs using Synopsys tools and Cadence tools. The third day of the course dealt with the H-SPICE tool from Cadence which helps in spice modeling of Integrated Circuits. Practice session was given for practicing the topics learnt during 3 days of the course. In the  valedictory ceremony participation certificates were distributed by Dr. Appu Kuttan K.K., Director, MANIT Bhopal. The course covering techniques of Analog/Digital IC Design benefited more than 60 participants.