ADVANCED VLSI DESIGN

Ms. Seema (Assistant Prof., ECE), along with Ms. Reva Nagi (Assistant Prof., ECE) of Dronacharya College of Engineering , Gurgaon conducted Summer School on “Advanced VLSI Design” from 27th June to 16th July 2016 in the college campus. Students have actively participated in the School.

The objective of the Summer School was to groom and empower students to make them self sufficient in the field of VLSI Design by giving them real time hands-on experience on Dsch, Microwind tool and XILINX tool and raise the technical skills of budding engineers and bridge the gap between industry and academia. It was best suited to beginners who were taking their first step towards VLSI Design. The Summer School was organized in collaboration with IETE, New Delhi.

The session started with the introduction of VLSI Design, Moore's law and the Gajaski's Y Chart for understanding of the different modeling designs of the VLSI Design from structural domain to physical domain. The block diagram of VLSI Design flow was explained in detail. Students got knowledge about Front End and Back End design in the VLSI world. Next introduction to Boolean algebra was explained. Students designed various expressions using CMOS. Static, Dynamic Power Dissipation and Noise Margin was explained in Digital IC Design. Different MOS Characteristics were briefed. Then introduction of combinational circuits of Digital Electronics, Half-Adder, Full-Adder and Multiplexer was explained and its CMOS schematics were designed. Pass transistor logic and transmission gate was also explained. No. of transistors get reduced when students designed the full-adder with transmission gate logic. In the end students were explained sequential circuits of Digital Electronics. Memory Cell and different Latches were also explained using CMOS. Latches were designed using Transmission gate. Students learnt how transmission gate logic can reduce the no. of transistors in any circuit. Differences between BJT and MOSFET were also briefed to the students. Fabrication mechanism of Depletion and Enhancement type MOSFET was explained. MOS Transistor model was elaborated.

Practical Session:

The session started with introduction of Dsch tool. The schematic of PMOS Switch, NMOS Switch was designed. A CMOS inverter was designed with the PMOS and NMOS and schematic of CMOS NAND gate and CMOS NOR gate was also designed and the timing waveform was along with the timing waveforms verification. Students solved various Boolean expressions and designed the schematic of Half-Adder, Full-Adder, Full-Adder Using Half-Adder, Multiplexer using transmission gate and verified the waveforms. Students designed Memory cell, S-R Latch, D-Latch using transmission gate and verified their timing waveforms.

Students were briefed about the different fabrication processes like Oxidation, Photolithography, Etching, Metallization etc. Rules of layout were explained with the help of stick diagram. Students designed CMOS NAND gate and CMOS NOR gate with stick diagram in groups and worked on delay optimization in various circuits i.e. Half-Adder, Full-Adder, Multiplexer and D-latch and completed their designs with different foundry and verified different timing diagrams. Later students were introduced to the Digital Systems and the basics required in designing them. The functioning of basic digital circuits such as Logic gates, Half Adder, Full Adder, Multiplexers, Encoders, Decoders etc. along with some Sequential Circuits such as Flip Flops, Registers, Counters etc. were discussed in detail. On the last day of the week students were introduced to VHDL as the Hardware Descriptive Language used to design the digital systems. and the design prospects such as Entity, Architecture, Package, Configuration etc. were also introduced. Students were given an overview of how to write a VHDL code for a particular design.

Practical session:

In the session, the layout of CMOS NAND and CMOS NOR was designed and output waveforms were verified. Hands on session on the circuits that were discussed in the theory session. Students learnt to construct entity and architecture for Full Adder and Multiplexer.

The session started with the discussion on Generics and Configuration. A brief structural description was given which described components and their interconnections. Discussing further students were explained each component type is associated with an ENTITY?ARCHITECTURE pair. The architecture contain other components whose type will then be associated with other ENTITY?ARCHITECTURE pairs. The students were introduced to the importance of Con?guration, which describes linkages between component types and ENTITY?ARCHITECTURE pairs. An outline of related declarations and design elements like subprograms and procedures were also given, which can be placed in a package for re-use. Next a detailed presentation on Synchronous Sequential Circuits which are also called as Finite State Machines. The behavior of these circuits was explained and development of practical design technologies was taught. The session also witnessed a discussion on a number of practical issues that arise in the design of real systems the solutions with which they can be overcome. Various examples of larger circuits which illustrated a hierarchical approach in designing digital systems were also discussed. On the last day of the week introduction of ROM, RAM and PLA was explained. Then, the PLD Devices i.e Programmable Logic Devices, FPGAs, CPLD and ASIC was discussed . Students learnt about the differences between the FPGA and CPLD and how the synthesis becomes complete with the burning of program in FPGA and CPLD kit.

Practical Session:

The session included writing of VHDL code for a Full Adder using structural architecture and rediscovering the use configuration and generics in it through various examples. VHDL codes for some real time digital systems such as Sequence Detector, Pulse Counter etc. were simulated. The students worked on various Moore and Mealy type FSM designs. The designing of Counters and Code Converters helped the students to understand the two kinds of FSM design styles in a much better manner. Designing of a Coin Vending Machine using FSM. Students also verified their program on FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device) kit.

Glimpses: