TALK BY PROF. PARTHA PRATIM PANDE

The IEEE Circuits & Systems/Control Society (CAS-CS), Delhi Chapter organized “ATalk by Prof. Partha Pratim Pande” at IIT Delhi, Hauz Khas, New Delhi on 16th October 2014. Eight students Shubham Chhabra (16150), Dishant Passi (16056), Priya Yadav (16955), Kavita Fulara (16080), Mansi (16089), Gaurav (16062), Mandisha (16085), and Brijesh (16044) from CSE Department attended the lecture.

Partha Pratim Pande is a Professor and holder of the Boeing Centennial Chair in computer engineering at the school of Electrical Engineering and Computer Science, Washington State University, Pullman, USA. He received his M.S degree in computer science from the National University of Singapore and the Ph.D. degree in electrical and computer engineering from the University of British Columbia, Vancouver, BC, Canada. His current research interests are novel interconnect architectures for multicore chips, on-chip wireless communication networks, and hardware accelerators for biocomputing. Dr. Pande currently serves as the Associate Editor-in-Chief (A-EIC) of IEEE Design and Test (D&T). He is on the editorial boards of ACM Journal of Emerging Technologies in Computing Systems (JETC) and Sustainable Computing: Informatics and Systems. He also serves in the program committee of many reputed international conferences. He has won the NSF CAREER award for his research on WiNoCs in 2009. He is the winner of the Anjan Bose outstanding researcher award from the college of engineering, Washington State University in 2013.

The speaker introduced a new topic in Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges. The continuing progress and integration levels in silicon technologies make complete end-user systems on a single chip possible. This massive level of integration makes modern multi-core chips all pervasive in domains ranging from weather forecasting, astronomical data analysis, and biological applications to consumer electronics and smart phones. NoCs have emerged as communication backbones to enable a high degree of integration in multi-core SoCs. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between far-apart blocks causes high latency and power consumption. The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. In this talk, Dr. Pande presented an overview of the various wireless NoC (WiNoC) architectures proposed so far designed in traditional 2D IC substrate.

After this, Dr. Pande introduced how high bandwidth and low power WiNoC architectures can be designed by incorporating the small-world architecture. He presented detailed performance evaluation and necessary design trade-offs for the small-world WiNoCs with respect to their conventional wireline counterparts. Dr. Pande also focused on different media access control (MAC) mechanisms and routing protocols used for planar WiNoCs so far. To sustain the predicted WiNoC performance, a deadlock-free routing algorithm must be designed. The routing protocol also needs to be simple without incurring excessive power, area and latency overheads. Dr. Pande also presented performance evaluation of WiNoCs with respect to various other emerging NoC architectures, like 3D, Photonics and RF-I.

It was a scholarly experience for all the attendees giving them the opportunity to gain a lot of knowledge on the topic. Dr. Partha Pratim Pande shared his knowledge with various researchers and students across the country. It was a very interactive session where sir held a Q&A round taking all the queries of the attendees at the end of the lecture.

Some Glimpse